Laminar enables TCP at terabit speeds on programmable switches

Rajath Shashidhara and co-authors have announced a research paper presenting Laminar, a TCP stack implemented for programmable RMT pipelines and prototyped on Intel Tofino 2, published on arXiv (v3, 7 Feb 2026).

• Main announcement: The paper presents Laminar, a TCP implementation for programmable RMT pipelines that retains standard TCP semantics and POSIX socket compatibility, using three techniques (optimistic concurrency, pseudo-segment injection, bump-in-the-wire processing) and demonstrates a prototype on Intel Tofino 2 with concrete results: saves up to 16 host CPU cores, 5× lower 99.99p tail latency, 2× better throughput-per-watt, and nearly 1 Bpps at 20 µs RPC tail latency.
• Background and details: The submission is an arXiv research paper (arXiv:2504.19058, DOI via DataCite) with a 16-page PDF and TeX source; Laminar matches RDMA performance for RPC and streaming (including NVMe-oF with SPDK), generalizes to FPGA SmartNICs, and reports a 3× improvement over ToNIC under equal timing. The content is an academic announcement of experimental results, not a commercial product release.