MIT develops stacked back-end transistors with integrated memory

MIT researchers have announced a new back-end-of-line integration platform that stacks ultra-thin indium-oxide transistors and ferroelectric memory directly on existing CMOS circuits to boost energy efficiency for computation-intensive tasks like generative AI.

• The team uses amorphous indium oxide grown at ~150°C on the chip back end to form ~2 nm-thick channel layers and ~20 nm memory transistors with ferroelectric hafnium-zirconium-oxide, achieving 10-nanosecond switching at lower voltages, enabling compact, energy-efficient logic-plus-memory stacks.
• The work, presented in two papers at the IEEE International Electron Devices Meeting and supported by Semiconductor Research Corporation (SRC) and Intel, involves collaborators at MIT, the University of Waterloo, and Samsung Electronics, with fabrication at MIT Microsystems Technology Laboratories and MIT.nano, and aims toward integrating these back-end memory transistors into larger circuits and refining ferroelectric material control.