Low-power 2D CFETs using single-crystal high-κ dielectrics

The article reports a new materials and device demonstration from the authors: a wafer-scale single-crystal anatase titanium dioxide (A-TiO2) dielectric integrated with 2D semiconductors to build low-power CFETs and logic circuits.

• Main announcement: The authors fabricated a 3-inch freestanding A-TiO2 membrane and showed it can be van der Waals integrated with MoS2 and WSe2 to produce enhancement-mode FETs and vertically stacked CFET inverters with high gain and ultralow static power.
• Key results and context: The dielectric has κ ≈ 44–50 at 18.2 nm thickness, enables sub-1-nm EOT, and supports record-low hysteresis (about 1.5 mV) and subpicowatt static power; the paper also reports scalability projections to a 10 nm gate length and stable operation at 0.3 V.